发明名称
摘要 <p>A non-volatile memory has a plurality of word lines, a plurality of bit lines and a plurality of memory elements having stored information corresponding to electric charges accumulated at floating gates at the intersections of the plurality of word lines and the plurality of bit lines, and electrically performing operations to write and erase the stored information. A write control circuit for controlling the electric charges accumulated at the floating gates by performing a verify operation, after performing a write operation in a prescribed write quantity on the memory elements, carries out one or more each of search write operations, set to a smaller write quantity than the prescribed write quantity at the time of start of writing, and verify operations matching thereto.</p>
申请公布号 JP3922516(B2) 申请公布日期 2007.05.30
申请号 JP20000296023 申请日期 2000.09.28
申请人 发明人
分类号 G11C16/02;G11C11/56;G11C16/10;G11C16/16;G11C16/34 主分类号 G11C16/02
代理机构 代理人
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