发明名称 |
REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES |
摘要 |
<p>A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.</p> |
申请公布号 |
KR20070055569(A) |
申请公布日期 |
2007.05.30 |
申请号 |
KR20077006860 |
申请日期 |
2007.03.26 |
申请人 |
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. |
发明人 |
EROKHIN YURI;JEONG, U KYO;SCHEUER JAY T.;WALTHER STEVEN R. |
分类号 |
H01L21/225;H01L21/265;H01L21/336;H01L29/78 |
主分类号 |
H01L21/225 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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