发明名称 Redundancy circuits for semiconductor memory
摘要 A semiconductor random access memory device has an array of normal memory and an array of dummy memory cells. The array of the dummy memory cells are controlled in order to form a redundant twin-cell structure that includes at least one of the dummy memory cells.
申请公布号 US7224626(B2) 申请公布日期 2007.05.29
申请号 US20050108179 申请日期 2005.04.18
申请人 INFINEON TECHNOLOGIES AG 发明人 OH JONG-HOON
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
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