发明名称 Strombegrenzungsempfänger mit Impedanz- /Lastanpassung für einen Empfängerchip in abgeschaltetem Zustand
摘要 The inventive mechanism prevents current flow from the drain 12 to the source 11 and substrate 13, in a power off condition of a p-type FET. The current flow from the drain to the substrate is prevented by raising the voltage required to turn on the diodes that are formed when the power is off. This is accomplished by having the substrate gate connected to a series of diodes 15 formed from other pFET devices. The combined threshold voltage of the series exceeds a voltage associated with the current. The current flow from the drain to the source is prevented by pinching off 26, 27 the channel of the pFET during a power off condition. Since a high signal is required to turn off a pFET device and the power to the pFET is off, an off chip voltage associated with the current is used to turn off the pFET. A current sink FET 38 is used to prevent reflections by supplying the proper impedance to receive the off chip signal associated with the current. <IMAGE>
申请公布号 DE69933319(T2) 申请公布日期 2007.05.10
申请号 DE1999633319T 申请日期 1999.03.03
申请人 AGILENT TECHNOLOGIES INC. (N.D.GES.D.STAATES DELAWARE) 发明人 SHEPSTON, SHAD R
分类号 H01L27/04;H03K19/003;H01L21/822;H01L21/8234;H01L27/088;H03K19/00 主分类号 H01L27/04
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