发明名称 TEST METHOD AND TEST APPARATUS
摘要 PROBLEM TO BE SOLVED: To suppress a supply voltage overshoot occurring at the same time as the termination of a function test for a semiconductor integrated circuit device. SOLUTION: After a function test process, dummy test data is supplied to the semiconductor integrated circuit device to perform a post-processing process, at which a clock speed is gradually reduced. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007108016(A) 申请公布日期 2007.04.26
申请号 JP20050299200 申请日期 2005.10.13
申请人 FUJITSU LTD 发明人 WATANABE TAKAO;ISHIHARA SHIGENOBU
分类号 G01R31/28;H01L21/66 主分类号 G01R31/28
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