| 摘要 |
The present invention provides a data processing system, a method, and a computer program product for stopping at least two clock signals that oscillate at different frequencies and restarting the at least two clock signals at their correct phase. A RUNN counter stops the at least two clock signals. The RUNN counter stops the faster clock signal and restarts the faster clock signal at the correct phase. A phase status circuit determines the phase where the slower clock signal stopped and produces a phase status signal. A second circuit utilizes the phase status signal to start the slower clock signal at the correct phase. Therefore, the present invention insures that the faster clock signal and the slower clock signal are restarted at the correct phase. In another embodiment, the second circuit enables the present invention to start the slower clock signal at a desired phase.
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