MEMORY USING HOLE TRAPPING IN HIGH-K DIELECTRICS

摘要

A non-volatile memory is described having memory cells with a gate dielectric (312) . The gate dielectric is a multilayer charge trapping dielectric between a control gate (310) and a channel region (308) of a transistor to trap positively charged holes. The multilayer charge trapping dielectric comprises at least one layer of high-K. A backgate (306) forms a p-n junction with the substrate (300) .