发明名称 |
Packet management device for fast-packet network |
摘要 |
<p>In a fast-packet network, incoming HDLC data are supplied by a receiving line interface device to a packet management device comprising a receiving state machine that shifts the data through a DLCI extractor. The extracted DLCI is used as an address indicating a location of a translation RAM that stores the destination DLCI and control data corresponding to the incoming HDLC data. The destination DLCI replaces the current DLCI field of the incoming data. A frame control state machine requests a frame buffer of a frame buffer RAM to be allocated to the incoming HDLC packet and writes the data to the allocated buffer. Simultaneously, a packet availability message is sent to the destination packet management device indicated by the control data in the translation RAM. A transmitting circuit of the destination packet management device has a transmitting state machine that rewrites the HDLC data from the frame buffer RAM to a FIFO register. When the FIFO register is full or entire data frame is in the FIFO register, the data are transferred to an HDLC transmitter coupled to a transmitting line interface device.</p> |
申请公布号 |
EP0676879(B1) |
申请公布日期 |
2007.04.25 |
申请号 |
EP19950300390 |
申请日期 |
1995.01.23 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
THOR, ALLEN |
分类号 |
H04L12/56;H04Q3/52;H04L29/06;H04L29/08;H04Q11/04 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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