发明名称 Memory tiling architecture
摘要 A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.
申请公布号 US7207026(B2) 申请公布日期 2007.04.17
申请号 US20040990237 申请日期 2004.11.16
申请人 LSI LOGIC CORPORATION 发明人 ANDREEV ALEXANDRE;VIKHLIANTSEV IGOR;PAVISIC IVAN
分类号 G06F17/50;H03K19/00 主分类号 G06F17/50
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