摘要 |
<p>A high speed integrated logic test circuit for self test use has outputs fed back (19, 20) to inputs (2, 3) and both inputs and outputs (4, 5) connected to core input output interface logic (7. 9) between a test pattern generator (26) and Multiple Input Shift Register (28) test pattern analysis logic integrated in the core, input or output logic. Independent claims are included for high speed integrated logic test procedures using the circuit.</p> |