发明名称 DELAY CIRCUIT AND VIDEO SIGNAL PROCESSING CIRCUIT EMPLOYING SAME
摘要 PROBLEM TO BE SOLVED: To provide a delay circuit utilizing a switched/capacitor for decreasing a parasitic capacitance between a drain and a substrate, and to provide a video signal processing circuit employing the delay circuit. SOLUTION: The delay circuit includes: a switched-capacitor group including a plurality of switched-capacitor sections each including charging/discharging transistors and a capacitive element connected to the sources of the transistors wherein an input signal is given to each of the drains of the charging transistors in common and the charging transistors are connected to charge the capacitive elements, the discharging transistors are connected to discharge the capacitive elements from each of the drains and to output an output signal; and a switching control section that controls ON/OFF of the gates of the charging/discharging transistors to sequentially charge the capacitive elements on the basis of the input signal and to sequentially output the output signal by discharging the capacitive element having previously been charged in the sequential charging, and in the two switched-capacitor sections adjacent to each other, both the charging/discharging transistors are arranged adjacent to each other and the drains of both the charging/discharging transistors are connected in common. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007097019(A) 申请公布日期 2007.04.12
申请号 JP20050286081 申请日期 2005.09.30
申请人 SANYO ELECTRIC CO LTD 发明人 SERIZAWA SHUNSUKE;SAKATA TETSUO;MEYA MASATO
分类号 H04N9/64;H03H11/26 主分类号 H04N9/64
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