发明名称 Method and Apparatus for Processing Financial Information at Hardware Speeds Using FPGA Devices
摘要 A method and apparatus are disclosed for using decision logic deployed on a reconfigurable logic device to process a stream of financial information at hardware speeds. The decision logic can be configured to perform data reduction operations on the financial information stream. Examples of such data reductions operations include data processing operations to compute a latest stock price, a minimum stock price, and a maximum stock price.
申请公布号 US2007078837(A1) 申请公布日期 2007.04.05
申请号 US20060561615 申请日期 2006.11.20
申请人 WASHINGTON UNIVERSITY 发明人 INDECK RONALD S.;CYTRON RON K.;FRANKLIN MARK A.;CHAMBERLAIN ROGER D.
分类号 G06F3/06;G06F17/30;G06F11/00 主分类号 G06F3/06
代理机构 代理人
主权项
地址