发明名称 |
Chip-area reduction and congestion alleviation by timing-and-routability-driven empty-space propagation |
摘要 |
An EDA (Electronic Design Automation) process which collects and moves empty-spaces among cells on a circuit layout to one or more target areas for productive use, such as chip-size reduction and routability congestion alleviation. The process includes globally moving the empty-spaces to the target area and thereafter locally moving the empty-spaces as refinement.
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申请公布号 |
US7200827(B1) |
申请公布日期 |
2007.04.03 |
申请号 |
US20040843791 |
申请日期 |
2004.05.11 |
申请人 |
APEX DESIGN SYSTEMS, INC. |
发明人 |
KU TSU-WEI;FANG WEN-CHUNG |
分类号 |
G06F9/45;G06F17/50 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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