发明名称 Receiver and method for mitigating temporary logic transitions
摘要 A circuit and method for receiving data signals over a data signal line are disclosed. In one embodiment, a receiver circuit is provided for receiving data signals transmitted over a signal line. The receiver circuit comprises an inverter circuit having an input that forms an input of the receiver circuit and an output coupled to an internal node, an output circuit having an input coupled to the internal node and an output that provides an output of the receiver circuit, and a charge adding circuit that provides at least a portion of a temporary logic transition at the input of the receiver circuit, induced by a logic transition on an adjacent signal line, to the internal node to mitigate erroneous logic transitions associated with the receiver circuit.
申请公布号 US7200821(B2) 申请公布日期 2007.04.03
申请号 US20040089576 申请日期 2004.06.07
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 WANG LEI;FETZER ERIC S.
分类号 G06F17/50;H03K17/00;H03K19/003;H04L25/02 主分类号 G06F17/50
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