| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To attain increase of a read/write speed of data and reduction of power consumption by allowing a gate length of a memory cell to be shortened while reducing a potential difference between a source and a drain, and also by eliminating such a problem that charge/discharge of a comparatively larger electric charge arise during the verify operation after a write-in (program) of bit data is carried out with respect to the memory cell. <P>SOLUTION: At t7 of program operation, 4V is applied on a cell well of a selective memory cell, 0V is applied on the drain, 10V is applied on the gate and Vcc is applied on the source respectively, and at t13 of subsequent verify operation, a selective word line WL is settled to -5V while keeping the voltage of the cell well to 4V as it is. The WL then is kept to be set at a voltage (-5V) having a higher absolute value than that of a voltage at the normal read-out. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
