发明名称 METHOD AND APPARATUS FOR TOLERANCE OF LOST TIMER TICKS DURING RECOVERY OF A MULTI-PROCESSOR SYSTEM
摘要 <p>A method and apparatus for detecting and tolerating situations in which one or more processors in a multi-processor system cannot participate in timer-driven or timer-triggered protocols or event sequences. The multi-processor system includes multiple processors each having a respective memory. These processors are coupled by an inter-processor communication network (preferably consisting of redundant paths). Processors are suspected of having failed (ceased operations) outright or having a failed timer mechanism when other processors detect the absence of periodic "IamAlive" messages from other processors. When this happens, all of the processors in the system are subjected to a series of stages in which they repeatedly broadcast their status and their connectivity to each other. During the first such stage, according to the present invention, a processor will not assert its ability to participate unless its timer mechanism is working. It arms a timer expiration event and does not assert its health until and unless that timer expiration event occurs.</p>
申请公布号 EP1012718(B1) 申请公布日期 2007.03.14
申请号 EP19980904696 申请日期 1998.01.27
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 BASAVAIAH, MURALI;KRISHNAKUMAR, KAROOR, S.;MURTHY, SRINIVASA, D.
分类号 G06F11/00;G06F11/20;G06F11/14 主分类号 G06F11/00
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