发明名称 Viterbi decoder
摘要 A path storing circuit has path holding parts at a plurality of stages storing a survivor path and corresponding to times. A majority decision circuit receives output values of three delay circuits including the top and bottom delay circuits each receiving a selected output of a selector out of six delay circuits in the path holding part at the final stage and makes a decision by a majority.
申请公布号 US7187729(B2) 申请公布日期 2007.03.06
申请号 US20030339321 申请日期 2003.01.10
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 NAGANO KOUICHI
分类号 G06F11/10;H03D1/00;H03M13/23;H03M13/41;H03M13/43;H04L1/00 主分类号 G06F11/10
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