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发明名称
快闪记忆体元件中之选择性的缓慢程式化收敛
摘要
复数个记忆单元系以增量地增加的程式化脉冲施加到记忆单元所耦接的字线而被程式化。在每个脉冲之后,一个验证动作系判断每个单元的临界电压。当该临界电压到达一个验证前的临界值时,只有连接至该特定的单元之位元线被偏压一中间的电压,该中间的电压系减缓该单元的Vt上之改变。其它的单元系继续以其正常的步调而被程式化。当每个单元的Vt到达该验证前的位准时,其系被偏压该中间的电压。当其临界电压到达验证电压的临界值时,所有的位元线系被偏压一禁止电压。
申请公布号
TW200709209
申请公布日期
2007.03.01
申请号
TW095121156
申请日期
2006.06.14
申请人
麦克隆科技公司
发明人
米契尔 因卡纳堤;吉欧瓦尼 圣廷;唐曼索 凡里
分类号
G11C16/04(2006.01)
主分类号
G11C16/04(2006.01)
代理机构
代理人
桂齐恒;阎启泰
主权项
地址
美国
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