发明名称 Method and system for cache power reduction
摘要 A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After accessing each tag array, a selected data array is identified, and subsequently activated. At least one predetermined data entry from the activated data array is accessed, wherein all other data arrays are deactivated during the read operation. In another example, the cache memory is divided into multiple sub-groups so that only a particular sub-group is involved in a memory read operation. By deactivating any many circuits as possible throughout the read operation, the power consumption of the cache memory is greatly reduced.
申请公布号 US7177981(B2) 申请公布日期 2007.02.13
申请号 US20030434617 申请日期 2003.05.09
申请人 VIA-CYRIX, INC. 发明人 DAVIS TIMOTHY D.
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
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