Power efficient cycle stealing

摘要

Arrangements and methods to cycle steal and reduce power consumption in an integrated circuit are disclosed. Embodiments of the invention exploit the art of cycle stealing for increased system performance, while facilitating a more power efficient bypass mode when power conservation is desired over performance. One embodiment includes a network of integrated delay elements employing a multiplexor to transfer either a normal or a delayed clock signal to a clock splitter. Another embodiment includes a network of delay elements, configured to enable or disable power conservation. A further embodiment integrates a configurable delay circuit into a clock splitter arrangement.