| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processing system and a memory controller capable of suppressing the increase of the number of cycles due to access to data whose access is not requested. SOLUTION: This information processor is provided with: memories M<SB>0</SB>to M<SB>n-1</SB>grouped into a first memory group G1 and a second memory group G2; a data processor 10 for outputting an access request to the memories M<SB>0</SB>to M<SB>n-1</SB>; and a memory controller 20 including an address calculating circuit 21 for calculating a second address f(A) by using a first address A included in the access request and a control part 22 for outputting a first control command Cmd(A) for controlling the operation of the first memory group G1 to be accessed by the first address A and a second control command Cmd(f(A)) for controlling the operation of the second memory group G2 to be accessed by the second address f(A) in different cycles. Data transfer between the memories M<SB>0</SB>to M<SB>n-1</SB>and the data processor 10 is controlled by the memory controller 20. COPYRIGHT: (C)2007,JPO&INPIT
|
