发明名称 FORMING METHOD OF MARK FOR CHECKING MISALIGNMENT AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a forming method of a mark for checking a misalignment which can improve the measurement accuracy in an alignment deviation check by faithfully reflecting an amount of transfer positional deviation of a device pattern. <P>SOLUTION: In a reference layer, a reference layer device pattern and first marks existing in the same layer as the reference layer device pattern are formed. In an upper layer above the reference layer, an upper layer device pattern corresponding to the reference layer device pattern is formed and a second mark region consisting of an arrangement of a plurality of patterns 320a-326a which is in the same layer as the upper layer device pattern and is the same as the upper layer device pattern in terms of at least a line width, a pitch, and a pattern density is formed adjacently to the first marks. Then, the patterns 320a and 326a arranged in the boundary portion of the second mark region are selectively removed to form second marks consisting of the remaining patterns 321a-325a. Using the first and second marks, a misalignment deviation between the patterns in the reference layer and the upper layer is checked. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007035768(A) 申请公布日期 2007.02.08
申请号 JP20050214201 申请日期 2005.07.25
申请人 TOSHIBA CORP 发明人 SATO TAKASHI
分类号 H01L21/027;G03F1/42 主分类号 H01L21/027
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