| 摘要 |
A delay locked loop for generating an internal clock signal locked to an external clock signal includes: a phase detector for detecting a phase difference between the external clock signal and the internal clock signal; a delay unit controller for generating a control signal and a selection signal in response to an output signal of the phase detector; a variable delay device (VDD), responsive to the control signal and a selection signal, to produce a delayed version of the external clock signal on a VDD output line, the variable delay device being configured such that, if the external clock signal undergoes a change from a first frequency to a second frequency significantly different than the first frequency, then a resultant load on the VDD output line nonetheless remains substantially the same.
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