| 摘要 |
There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is proposed that in the memory module ( 100 a , 100 b , 100 c , 100 d) a command and write data signal (CA, WD) is received and a read data signal (RD) is transmitted from the memory module ( 100 a , 100 b , 100 c , 100 d). Further, an input clock signal (CLK) is received in the memory module ( 100 a , 100 b , 100 c , 100 d) and is regenerated by means of a clock synthesizer unit ( 150 ) of the memory module ( 100 a , 100 b , 100 c , 100 d) to produce a regenerated input clock signal of the memory module ( 100 a , 100 b , 100 c , 100 d). The read data signal (RD) transmitted from the memory module ( 100 a , 100 b , 100 c , 100 d) is synchronized to the regenerated input clock signal of the memory module ( 100 a , 100 b , 100 c , 100 d). For this purpose, the clock synthesizer unit ( 150 ) preferably comprises a phase-locked loop.
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