STRUCTURE OF CHIP-INSERT TYPE INTERMEDIATE SUBSTRATE, MANUFACTURING METHOD THEREOF, WAFER LEVEL LAMINATION STRUCTURE OF HETEROGENEOUS CHIP USING THE SAME, AND PACKAGE STRUCTURE

摘要

PROBLEM TO BE SOLVED: To provide a technology of vertically laminating heterogeneous chips in various kind, with no limit on difference in chip size.

SOLUTION: A wafer level lamination technology is disclosed for heterogeneous chips 140a, 140b, and 140c of different size, as well as a package manufacturing technology using the same. Chip-insert type intermediate substrates 100a, 100b, and 100c of the same size are used to form the lamination structure of the heterogeneous chips 140a, 140b, and 140c at wafer level, which is cut to provide a package. The chip-insert type intermediate substrates 100a, 100b, and 100c are manufactured by forming a cavity 130 on a silicon substrate as a wafer, and forming a through-via 120 on the silicon substrate around the cavity 130. Then a chip is inserted in the cavity 130 to form a re-wiring conductor 150 that connects the chip with the through-via 120.

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