发明名称 TIMING ANALYZING CIRCUIT AND NET LIST FORMING METHOD
摘要 PROBLEM TO BE SOLVED: To easily analyze the possessing required timing by using a static timing analyzing tool, in a combination circuit (for example, a gated clock cell) in a semiconductor LSI. SOLUTION: A setup and hold analysis can be performed by the static timing analyzing tool, by connecting a timing analyzing register to the combination circuit being an analytical object. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007004695(A) 申请公布日期 2007.01.11
申请号 JP20050186841 申请日期 2005.06.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 UEDA YOSHINOBU;SOKAWA YASUYO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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