发明名称 Network packet buffer allocation optimization in memory bank systems
摘要 An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.
申请公布号 US7158438(B2) 申请公布日期 2007.01.02
申请号 US20050092010 申请日期 2005.03.29
申请人 INTEL CORPORATION 发明人 KUO CHEN-CHI;ARUNACHALAM SENTHIL NATHAN;LAKSHMANAMURTHY SRIDHAR;NAIK UDAY
分类号 G11C8/00;G11C7/10 主分类号 G11C8/00
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