| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a microprocessor and communication method with which a processor is efficiently operated and a reply of good response can be returned to a transmitting side microprocessor by reducing, as little as possible, interruption to a CPU that occurs when a microprocessor connected by a network receives a packet from the network. <P>SOLUTION: A microprocessor 3 comprises a CPU and a communication module. The communication module includes a register 22 for storing information managed by the microprocessor 3. The communication module compares information on a prescribed bit position within a packet input via a network with information held in the register and judges whether the CPU is to perform processing corresponding to packet reception in accordance with a comparison result. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
