| 摘要 |
A method for manufacturing a semiconductor device is provided to reduce contact resistance and to increase a contact area between a bit line and a storage node by additionally growing a landing plug to recover a step difference. An interlayer dielectric(27) is formed on a semiconductor substrate(21) where plural gates(25) are formed. The interlayer dielectric is etched to form a contact hole exposing the gates and a substrate region between them. An amorphous silicon layer is formed on the resultant structure to gap-fill the contact hole. The amorphous silicon layer is annealed to be single-crystallized. CMP is performed on the single-crystallized silicon layer to form a landing plug(31) between the gates. SEG(Selective Epitaxial Growth) process is performed on the substrate resultant structure to grow a single crystal silicon on a surface of the landing plug.
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