| 摘要 |
The output capacitance of an FET electronic device such as a MESFET or HEMT device operating in high efficiency modes, in particular a power device, is increased in order to present a low impedance to harmonics, particularly the second harmonic. The device includes an electrically isolating layer 10 formed on a conductive p-type semiconductor layer which comprises a p-type GaAs layer 4 and a p+ InGaAs layer 6. The isolation layer includes an aperture 12 through which electrical connection to the p+ layer can be made and further transistor layers are formed on the isolating layer, for example source electrodes 14, drain electrodes 16, gate electrodes 20 and a silicon nitride passivating layer 22. The electrically conductive p-type layer provides capacitive coupling between the source electrode and the drain electrode. |
