发明名称 Resonance reduction arrangements
摘要 Resonance reduction arrangements to reduce the impact of power supply resonance on circuits, comprising a resonance sensor and a charge dumper, wherein upon the detection of the predetermined resonance by the resonance sensor at a circuit location, the charge dumper dumps charges at least one of from and to the circuit location, wherein the charge dumper comprises at least one gating transistor to dump the charges, the at least one gating transistor is directly connected to a first power supply line having a first potential and a second power supply line having a second potential of a different potential than the first potential.
申请公布号 US7143381(B2) 申请公布日期 2006.11.28
申请号 US20020331649 申请日期 2002.12.31
申请人 INTEL CORPORATION 发明人 ZHAO CANGSANG;TAYLOR GREG
分类号 G06F17/50;H01L21/98;H03K17/16;H03K17/30;H03K19/003 主分类号 G06F17/50
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