发明名称 TEST METHOD, TEST CIRCUIT, TEST CIRCUIT INTEGRATING DEVICE, AND COMPUTER PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a test circuit integrating device capable of reducing a test time, and generating no problem of voltage drop. SOLUTION: In the test circuit integrating device 100 for integrating a test circuit in a user circuit including a plurality of blocks, the test circuit 150 includes a phase generation circuit 152 for generating a test pattern for executing a phase test of each block of the user circuit, a retention count circuit 154 for calculating a retention test time to be considered when the test pattern is generated by the phase generation circuit, and a comparison circuit 156 wherein the test pattern is applied to each block of the user circuit, for comparing an expected value to the test pattern with an output value from each block, and the test circuit 150 is characterized by executing serially the phase test of each block, and executing the retention test just after the phase test relative to each block. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006317281(A) 申请公布日期 2006.11.24
申请号 JP20050140121 申请日期 2005.05.12
申请人 OKI ELECTRIC IND CO LTD 发明人 NOZAKI YASUHIRO;USHIKUBO MASANORI
分类号 G01R31/3183;G01R31/28 主分类号 G01R31/3183
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