发明名称 Method and apparatus for improved clock preamplifier with low jitter
摘要 A clock signal preamplifier comprises complementary pairs of differentially coupled transistors, with an output signal coupled to an inverter further comprising a totem-pole arrangement of complementary MOSFET transistors. The input signal to the preamplifier is typically sinusoidal, and the output signal is rectangular. Preferably, the differentially coupled transistors are bipolar, and a pair of diode damper circuits with bipolar transistors is preferably coupled to the complementary pairs of differentially coupled transistors. A reference voltage source is coupled to the control terminals of the damper transistors. A reference voltage source, which preferably comprises a totem-pole arrangement of complementary MOSFET transistors with its output node is coupled to its input node, provides a reference voltage for the diode damper circuits. Preferably, MOSFET transistors of the reference voltage source and MOSFET transistors of like kind of the inverter are configured to have substantially identical threshold voltages.
申请公布号 US2006255859(A1) 申请公布日期 2006.11.16
申请号 US20050125960 申请日期 2005.05.10
申请人 ZANCHI ALFIO;CORSI MARCO 发明人 ZANCHI ALFIO;CORSI MARCO
分类号 H03F3/16 主分类号 H03F3/16
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