发明名称 Semiconductor device manufacture method capable of supressing gate impurity penetration into channel
摘要 A gate electrode is formed above an n-type well including an n-type threshold voltage adjustment region, ions of p-type impurity are implanted with a low acceleration energy to form extension regions in the n-type well on both sides of the gate electrode, side wall spacers are formed on the side walls of the gate electrode, ions of p-type impurity are implanted with a small dose causing substantially no abnormal tailing in the gate electrode and with a relatively high acceleration energy to form p-type source/drain regions deeper than the threshold adjustment region, ions of atoms are implanted into the semiconductor substrate to change the upper parts of the gate electrode and the source/drain regions to amorphous state, ions of p-type impurity are implanted with a large dose to form high-concentration parts in the source/drain regions, and the impurities introduced by the ion implantation are activated.
申请公布号 US7135393(B2) 申请公布日期 2006.11.14
申请号 US20050118370 申请日期 2005.05.02
申请人 FUJITSU LIMITED 发明人 TAGAWA YUKIO
分类号 H01L21/265;H01L21/28;H01L21/3205;H01L21/336;H01L21/425;H01L21/8238;H01L29/08;H01L29/78;H01L31/109 主分类号 H01L21/265
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