| 摘要 |
PROBLEM TO BE SOLVED: To reduce a time necessary for delay calculation of a structured ASIC wherein a clock circuit is integrated to reduce a TAT of a design of the structured ASIC. SOLUTION: This delay calculation device is a device for performing the delay calculation of the structured ASIC (1) wherein the clock circuit (5) is integrated in a master slice (2, 3). The delay calculation device has: a storage device (14) holding a clock circuit delay library (17) storing clock circuit delay data obtained by the delay calculation of the clock circuit; and a delay calculation means (11, 16) performing the delay calculation of the structured ASIC 1 including the clock circuit (5), and generating delay calculation result data of the structured ASIC (1). The delay calculation means (11, 16) takes out at least partial data of the clock circuit delay data from the clock circuit delay library (17), and merges them to the delay calculation result data. COPYRIGHT: (C)2007,JPO&INPIT
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