| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock correction circuit, capable of reducing the cost by simplifying processing on software. <P>SOLUTION: The clock correction circuit for inputting a main clock A and a sub-clock B lower in frequency than the main clock A and outputting the main clock A while correcting the error of the frequency thereof comprises a pulse number counter 201 counting the pulse number of the main clock A contained in one cycle of the sub-clock B, an arithmetic part 203 calculating correction information using the pulse number counted by the counter 102 and a predetermined reference pulse number; a stopping signal counter 204 outputting a clock correction signal based on the correction information; and a gate 205 correcting the output of the main clock A based on the clock correction signal. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
