| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock control circuit allowing for easy switching of a frequency and timing and selection of a clock signal of less operation noise. <P>SOLUTION: The clock control circuit is provided with: a frequency dividing part (21 to 24) for dividing a master clock signal CLK at its falling timing to generate a frequency-divided clock signal DCK: a multiplication part (25 to 29) for multiplying by n at the rising timing of the master clock signal CLK and thinning an n-th clock pulse to generate a multiplied clock signal MC1: and a selection part (30 to 35) for selecting a bus clock signal BCK according to selection signals SL1 to SL3 from among the multiplied clock signals at various kinds of timing derived from the multiplied clock signal MC1 or a frequency dividing clock signal DCK to supply a processor 11 or the like with it. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
