| 摘要 |
A semiconductor memory device is provided to improve fail detecting capability by varying a voltage applied to a dummy region in fail detection. A semiconductor memory device includes a dummy bit line power supply line and a power supply line in a main cell, and a power supply unit for supplying different voltage level to the dummy power source line at a normal mode or a test mode. The power supply unit further includes a first power source for supplying 1/2 Vdd to the dummy bit line in the normal mode, a second power source for supplying Vdd to the dummy bit line in the test mode, and a third power source for supplying Vss to the dummy bit line in the test mode.
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