BUILT-IN SELF TEST METHOD AND APPARATUS FOR JITTER TRANSFER, JITTER TOLERANCE, AND FIFO DATA BUFFER

摘要

A transceiver (100) includes a serializer (102) that receives parallel data and generates serial data and a deserializer that receives serial data and receives parallel data. The transceiver (100) can be tested by generating a serialization clock (e.g., at clock generator (106)) and adding jitter to the clock in a known and controlled manner. The test signals can then be transmitted using the serialization clock. After the test signals are recovered by the clock and data recovery mechanism (e.g., with deserializer (104) and clock generator (108)). To test for jitter tolerance, the bit stream verifier (120) can be used to compare the recovered sequence to the original sequence. Preferably, each of these steps is performed on chip. In other aspects, a jitter transfer test and/or a FIFO test can be performed.