| 摘要 |
<p>The present invention relates to a system (50) for constructing and deconstructing data packets, wherein the system (50) is operable to support a number of different coding formats. The system (50) comprises a processor means (52), a to the processor means (52) connected processor bus (54), a to the processor means (52) connected packet processing data path (56) which is attached to the processor bus (54) as a slave via a bus interface means (58). The packet processing data path (56) comprises a number, n, of blocks (56 1 ,...; 56 n ), wherein n is an integer, and n=2. Each block (56 1 ,...; 56 n ) comprises configuration registers operable to provide information on what operation the block (56 1 ,...; 56 n ) should perform for the current packet field being processed. The bus interface means (58) comprises a first register (58 1 ) operable to control a bus of Update Enable signals, which bus also are connected to each of the n blocks (56 1 ,...; 56 n ). The bus interface means (58) also comprises a second register (58 2 ) operable to control a Mode signal, which also are connected to each of the n blocks (56 1 ,...; 56 n ). An Update Mode signal is connected to the bus interface means (58) and to each of the n blocks (56 1 ,...; 56 n ). A write to the second register (58 2 ) causes the Update Mode signal to be pulsed active, triggering the enabled configuration registers to update their values.</p> |
