发明名称 |
Flash/dynamic random access memory field programmable gate array |
摘要 |
A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
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申请公布号 |
US7120079(B2) |
申请公布日期 |
2006.10.10 |
申请号 |
US20050113286 |
申请日期 |
2005.04.21 |
申请人 |
ACTEL CORPORATION |
发明人 |
MCCOLLUM JOHN;BELLIPPADY VIDYA;BAKKER GREGORY |
分类号 |
G11C7/00;G11C8/00;G11C11/406 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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