发明名称 Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency
摘要 Logic circuits that provide improved efficiency are described. In one general embodiment, this is accomplished by feeding outputs of LEs in the logic circuit to multiplexers that receive their select signals from input terminals of the LEs in the logic circuit. In one embodiment, each of the LEs provides one output signal. The first LE in the logic circuit provides an output signal to one multiplexer, while each of the remaining LEs in the logic circuit provides an output signal to two multiplexers. In another embodiment, each of the LEs provides two output signals. The first LE in the logic circuit provides two output signals to one multiplexer, while each of the remaining LEs in the logic circuit provides two output signals to four multiplexers.
申请公布号 US7119575(B1) 申请公布日期 2006.10.10
申请号 US20040756206 申请日期 2004.01.12
申请人 ALTERA CORPORATION 发明人 SCHLEICHER JAMES;PEDERSEN BRUCE;KAPTANOGLU SINAN
分类号 H03K19/177 主分类号 H03K19/177
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