发明名称 |
Determining feasibility of IC edits |
摘要 |
A computer method of analyzing an integrated circuit ("IC") masked design data, comprising grouping into a cluster areas of layers preceding a target metal layer that are suitable for milling, deleting portions of the target metal layer that do not meet minimum tool spacing requirements to produce a modified metal layer, deleting portions of the modified metal layer that do not meet minimum design rule width requirements to produce a final metal layer, and comparing the final metal layer and the cluster to identify common areas.
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申请公布号 |
US7117476(B2) |
申请公布日期 |
2006.10.03 |
申请号 |
US20040861294 |
申请日期 |
2004.06.04 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
BACH JOHN M.;CARAWAN RAND B.;JOSHI HEMANT;THOMAS DAVID A. |
分类号 |
G06F17/50;G06F9/45;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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