| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit that can attain PLL locking in a short period of time, stably extract a clock, and can be compatible with high speed and broadbanding. <P>SOLUTION: The clock recovery circuit for extracting a clock whose frequency is equal to a data transmission speed from high speed transmission serial data, includes: an out of lock detector 8 for detecting out of locking from an output of a phase detector 4; a pull-in range detector 7 for detecting that an output frequency of a voltage-controlled oscillator 6 enters a pull-in range from the output of the phase detector 4; a frequency change circuit 9 for controlling a loop filter 5 to change the frequency of the voltage-controlled oscillator in accordance with outputs of the out of lock detector and the pull-in range detector; and a current source for supplying a current to a loop filter. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
