| 摘要 |
A frequency divider circuit for obtaining, from a plurality of first signals having a first frequency and being out-of-phase to each other, at least one second signal having a second frequency equal to a fraction of the first frequency. The frequency divider circuit includes a delaying block for each first signal, the delaying blocks being series-connected in a closed loop and having a signal input, a signal output connected to the signal input of a next delaying block in the closed loop, and a clock input for receiving the corresponding first signal. Each second signal is taken from the signal output of a corresponding delaying block.
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