| 摘要 |
A network node includes bidirectional interfaces having first ports for ingress/egress of circuit and/or packet based traffic from/to the network and second ports connected to a Hybrid Switch capable of routing mixed traffic through the node. The connection between the second ports and the Hybrid Switch is carried out by an unique SDH bus on the backplane which transport said mixed circuit and packet based traffic. An interface for mixed Ethernet packet and circuit based traffic forwards the VCs relevant to circuits to a combiner at the second port. For each packet entering the node the interface generates a VLAN-ID from the MAC addresses and maps it onto a CID identifier only usable inside the Hybrid Switch. A GFP framer inserts the CID in the GFP header and encapsulates the packet, without VLAN-ID, into the GFP payload. GFP frames so arranged are embedded into VC-4 containers, which are combined with the VCs relevant to circuits into an STM-16 flow directed to the Hybrid Switch. The latter receives and synchronizes all the m received STM-16 flows and for each flow disassembles the VCs and sends each byte of VCs carrying circuit based transport signal to an m -input multiplexer belonging to a Circuit Switch. For the VC-4s carrying packets, the Hybrid Switch sends each byte of n concatenated VC-4 to a set of m x m -input multiplexers belonging to a Packet Switch. The latter performs the delineation on the GFP frames, retrieves the CID and PLI contents from the header and sends their values to a Router. The m -input multiplexers both for circuits and packets are univocally associated to the m STM-16 input channels, so that all traffic node is considered simultaneously. The outputs of the m packet multiplexers are stored into m buffers to be sent together with the output of the circuit multiplexer to the inputs of a final multiplexer, whose output signal is sent to a STM-16 former followed by a serializer. Routing tables are stored in advance for packets and circuits. According to the routing tables, the Router of the Hybrid Switch, selects for the m circuit multiplexers the one out of m inputs to be forwarded to the output, while similar selection for the m packet multiplexers is performed from the received CIDs and PLIs values. The Centralized Router also controls the final multiplexer to output either packets or circuits. Finally, the VCs are completed with headers and pointers and the resulting STM-16 flows are forwarded on the SDH output bus towards the interfaces. The interfaces perform dual operations with respect of the former direction, particularly reinsert the VLAN-IDs in the payloads of the switched GFP frames.
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