| 摘要 |
The present invention is directed to a system for area efficient charge-based capacitance measurement requiring a minimum silicon area for probe pads. A structure block for the system includes several test structures coupled to a target test capacitance structure, a reference structure, and a logic block. Each test structure is coupled to a corresponding test capacitance structure. The logic block coupled to the several test structures selects a desirable test structure from the several test structures. The system may include several structure blocks and an additional logic block to select a desirable structure block. Each structure block includes a single output pin for busing each test output from the several test structures. In this manner, the silicon area may be minimized through reduction of the number of total pins and probe pads required.
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