发明名称 System and method for reducing the effects of clock harmonic frequencies
摘要 A system and a method are provided for reducing the effects of spurious frequencies in a wireless communications device. The system comprises a processor having a reference frequency input and a clock having an output connected to the processor input. The clock supplies a clock frequency, or reference frequency, to the processor. The reference frequency is the frequency at which the processor operates. The clock also has an input for selecting a reference frequency to provide to the processor. The system also includes a transceiver having a plurality of selectable communications passbands. If the wireless communications device is a telephone, for example, the transceiver frequency (passband) may change as a function of the mode in which the phone is operating (AMPS, PCS, GSM, CDMA, or W-CDMA). In response to changing operating modes (transceiver passband), the clock frequency is adjusted. The clock frequency is selected so that harmonic frequencies associated with the clock frequency do not substantially interfere with the transceiver passband.
申请公布号 US7103342(B2) 申请公布日期 2006.09.05
申请号 US20050205625 申请日期 2005.08.17
申请人 KYOCERA WIRELESS CORP. 发明人 KUSBEL PATRICK;TAN CHENG;CURTISS TROY
分类号 H04B1/00;H04B1/10;H04B15/00;H04B15/04;H04B15/06 主分类号 H04B1/00
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