发明名称 |
Memory cells with vertical transistor and capacitor and fabrication methods thereof |
摘要 |
Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.
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申请公布号 |
US2006175650(A1) |
申请公布日期 |
2006.08.10 |
申请号 |
US20050145862 |
申请日期 |
2005.06.06 |
申请人 |
NANYA TECHNOLOGY CORPORATION |
发明人 |
HUANG CHENG-CHIH |
分类号 |
H01L21/8244;H01L21/8234;H01L29/94 |
主分类号 |
H01L21/8244 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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