| 摘要 |
PROBLEM TO BE SOLVED: To reduce the influence of interruption on a CPU generated in DMA transfer of a result computed by a DSP, to a RAM. SOLUTION: An interface circuit is provided with an address change means capable of optionally changing high-order address values out of addresses connected with the CPU, and a DMA transfer control means for incorporating an interruption signal showing the termination of operation by the DSP, making a DMA transfer request to a DMAC and setting the high-order address values by the address changing means based on the interruption signal. The interface circuit is connected with the DSP (a transfer source), the RAM (a transfer destination) and the DMAC. In the interface circuit, only the first interrupt signal out of interrupt signals from the DSP (the transfer source) is responded to interrupt the CPU, and as to subsequent interrupt signals, the high-order addresses of the transfer source and transfer destination are forcibly changed by the address changing means to reduce the influence of interruption on the CPU. COPYRIGHT: (C)2006,JPO&NCIPI
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